The present disclosure relates to semiconductor process integration techniques. More specifically, it provides a method for forming self-aligned structures during the manufacturing of semiconductor devices.
Semiconductor device formation involves a series of manufacturing techniques related to the formation, patterning and removal of a number of layers of material on a substrate. As device linewidths continue to shrink, various individual processing steps require associated improvements. For example, as devices sizes shrink, layer thicknesses shrink and aspect ratios increase, the etch selectivity between one layer and another layer may need to increase accordingly. At times, as device criteria continue to shrink improvements to an individual processing step may not be sufficient to meet the desired device criteria. Thus, the integration of the overall process flow of the individual process steps also may be modified to provide a repeatable, stable process flow which satisfies shrinking device criteria.
One process integration technique utilized to satisfy demanding design criteria is the formation of self-aligned structures. The use of such self-aligned structures allows the formation of structures that may be smaller than the normal lithography or etch tolerances and allows tighter layer to layer alignment tolerances. Thus, as is known in the art, a variety of self-aligned techniques may be utilized to form structures such as self-aligned contacts or self-aligned gates. In some cases, the self-aligned process flow may utilize tone inversion photolithography masking techniques in which rather than defining the individual structures to be formed, the photolithography mask blocks an area that does not define one individual structure, again as is well known in the art. Such tone inversion processes provide a method to reduce damage to features in critical areas.